1. Field of the Invention
The present invention relates to a technique for improving the match of the electrical characteristics of MOS devices on an integrated circuit.
2. Description of the Prior Art
In certain integrated circuit applications, it is desirable to have two or more transistors with well-matched electrical characteristics. For example, in CMOS output buffers that provide ECL output levels (-0.9 to -1.7 volts), it is desirable to obtain a precise and well-controlled output level, in order to properly match the characteristics of the ECL bipolar devices. One type of ECL output buffer is shown in FIG. 4, wherein a reference MOS device M40 is provided, and the transistor M41 is used to set the level of the ECL "high" output voltage. Note that the gates of M40 and M41 are coupled together, by means of operational amplifiers 44, 45, and pass gate transistors M42, M43. It is desirable that the electrical characteristics of M40 and M41 be well-matched. (A comparable circuit may be used for setting the ECL "low" output voltage.) This type of output buffer is more fully described in U.S. patent application Ser. No. 371,356, filed June 26, 1989, and co-assigned herewith.
In another example, FIG. 5 illustrates a current mirror, wherein the gate and drain of a reference transistor M50 are connected together, with a current source causing a channel current Ia to flow. A "mirror" transistor M51 has its gate connected to the gate of the reference transistor, and the channel current Ib flowing though load R.sub.L will be equal, or proportional, to Ia, depending on the relative sizes of the transistors. To obtain precise control of Ib, the electrical characteristics (e.g., threshold and transconductance) of M51 should be the same as that of M50. More than one transistor can mirror the current in M50 in a similar manner. For an example of a current source having a current mirror, see U.S. Pat. No. 4,645,948 co-assigned herewith. However, the "reference" transistors of these examples (e.g., M40, M50) may be located on the integrated circuit at significant distances from the other transistors that should be matched to them (e.g., M41, M51). In these applications, the gate-to-source voltages of the matched transistors are identical, or nearly so.
It is recognized in the art that the location of a transistor on an integrated circuit can affect its characteristics. For example, the gate oxide thickness can vary over the surface of the integrated circuit. This can produce differences in the channel current that flows for a given gate-to-source voltage from one transistor as compared to another. For this reason, circuit and layout techniques have been developed to compensate for the differing transistor characteristics. For example, the "common centroid" configuration utilizes a group of four transistors arranged at the corners of a rectangle, with the diagonal pairs being connected in parallel. This effectively creates two transistor pairs, which may be used to implement a current mirror. The processing variations that are a function of placement (i.e., along the x and y axes of the broad surface of the chip) then largely cancel out. This is because each pair includes a transistor having the same x-axis location as one transistor of the other pair, and the same y-axis location as the other transistor of the other pair, thereby averaging out variations that are solely a linear function of position.
In addition, their are some process variations that result from orientation effects. For example, the ion beam implantation of source/drain regions may create shadowing effects that affect transistor performance, by changing the threshold voltage. This is discussed by R. W. Gregor in "Some Consequences of Ion Beam Shadowing in CMOS Source/Drain Formation", IEEE Electron Device Letters, Vol. EDL-7, No. 12, pp. 677-679 (1986). To negate such orientation-dependent effects, the prior art layout techniques required that matched transistors be oriented in the same direction, and with current flows in the same direction. However, such requirements limit design flexibility, and can complicate the layout process.